Shuang-Yuan Chen This email address is being protected from spambots. You need JavaScript enabled to view it.1, Mu-Chun Wang2 , Shao-Min Ho1 , Wei-Yi Lin1 , Yeh-Ning Jou3 and Heng-Sheng Haung1
1Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, Taiwan 106, R.O.C. 2Department and Institute of Electronic Engineering, Minghsin University of Science and Technology, Hsin Chu, Taiwan, R.O.C. 3Vanguard International Semiconductor Corporations, Hsin Chu, Taiwan, R.O.C.
Received: October 11, 2006 Accepted: January 25, 2008 Publication Date: December 1, 2008
In this work, laterally diffused MOS (LDMOS) transistors deployed with six layout parameters have been contrived and manufactured to prove the effectiveness of ESD protection using transmission line pulsing (TLP) measurements. The phenomena with high-current breakdown in ESD stress were observed and their electrical behaviors were analyzed to extract the optimal layout rules. After analyzing the ESD test results, the cardinal contributions of layout parameters affecting the trigger voltages of LDMOSs indicate the lateral buried layer length and the STI spacing. Additionally, non-uniform turn-on in the gate-grounded NMOS (GGNMOS) transistors, which would influence their ESD robustness, was observed by employing an EMMI (emission microscope) instrument. Through these analyses, the experimental results and the physical interpretations compose an important base on the design of using LDMOS transistors as ESD protection devices.
Keywords: Electrostatic Discharge (ESD), Transmission Line Pulsing (TLP), Laterally Diffused MOS (LDMOS)
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