A Radix-2 Non-Restoring 32-b/32-b Ring Divider with Asynchronous Control Scheme

Jen-Shiun Chiang; Eugene Lai; Jun-Yao  Liao

doi:10.6180/jase.1999.2.1.05

A Radix-2 Non-Restoring 32-b/32-b Ring Divider with Asynchronous Control Scheme

Electrical Engineering

Jen-Shiun Chiang¹, Eugene Lai¹ and Jun-Yao Liao¹

¹Department of Electrical Engineering Tamkang University Tamsui,251, Taiwan, R. O. C.

Received: April 12, 1999
Accepted: May 31, 1999
Publication Date: May 31, 1999

Download Citation: ||https://doi.org/10.6180/jase.1999.2.1.05

ABSTRACT

Division operation is very important in the computer system. Nowadays people use a hardware module─divider to implement the division algorithm. Conventionally synchronous techniques are applied to implement the divider. The synchronous systems always need system clock signals to trigger the system. However, the system clock of the synchronous system may cause some problems, such as clock skew, dynamic power consumption, ..., etc. Compared to synchronous systems, asynchronous circuits do not need system clock signals and thus the asynchronous system does not have the shortcomings mentioned above. Here we will propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is of simplicity and is very easy for the VLSI implementation. By this asynchronous architecture, we use TSMC’s 0.6um SPDM process to design a 32-b/32-b radix-2 non-restoring divider and the spice simulation proves it works. The HSPICE simulation shows that it can finish a 32-b/32-b division in between 3.7ns to 160.2ns.

Keywords: Asynchronous circuits, conditional carry-selection adder, divider, radix-2 non-restoring division algorithm, synchronous circuits, VLSI.

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