A Novel Architecture for High-Speed Viterbi Decoder

Yang-Han Lee; Yih-Guang Jan; Hsien-Wei Tseng; Ming-Hsueh Chuang; Chiung-Hsuan Peng; Wei-Tsong Lee; Chih-Tsung Chen

doi:10.6180/jase.2006.9.4.06

A Novel Architecture for High-Speed Viterbi Decoder

Yang-Han Lee This email address is being protected from spambots. You need JavaScript enabled to view it.¹, Yih-Guang Jan¹, Hsien-Wei Tseng¹, Ming-Hsueh Chuang¹, Chiung-Hsuan Peng¹, Wei-Tsong Lee¹ and Chih-Tsung Chen¹

¹Department of Electrical Engineering, TamKang University, Tamsui, Taiwan 251, R.O.C.

Received: May 9, 2005
Accepted: December 27, 2005
Publication Date: December 1, 2006

Download Citation: ||https://doi.org/10.6180/jase.2006.9.4.06

ABSTRACT

In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not only reduces its hardware connecting complexities in the unit but also improves the overall processing speed in the Viterbi decoder. We make analysis and comparison in the hardware complexities and processing speed between our proposed and conventional architectures in the Viterbi decoder

Keywords: Viterbi Decoder, Add-Compare-Select Unit (ACSU), Cyclic-Shift Register Unit (CSRU), Pseudo-Correlator Unit (PCU).

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