Journal of Applied Science and Engineering

Published by Tamkang University Press

1.30

Impact Factor

2.10

CiteScore

Hanru Zhang1 and Xiuhan Li This email address is being protected from spambots. You need JavaScript enabled to view it.1

1Institute of Electronic and Information and Engineering, Beijing Jiaotong University, Beijing, P.R. China


 

Received: July 18, 2013
Accepted: May 12, 2014
Publication Date: June 1, 2014

Download Citation: ||https://doi.org/10.6180/jase.2014.17.2.03  


ABSTRACT


A method utilizing Mason’s rule to derive the poles and zeros of the analog integrated circuits (IC) system separately based on the signal-flow graphs (SFG) is described in this paper. The numerator and denominator of transfer function can be derived separately through simple addition and subtraction to the forward-path gains and the loop gains of the SFG by this method. Besides, the poles and zeros can be obtained by some critical loop gains and forward-path gains. The number of the nontouching loops observed intuitively from the SFG determines the order of the transfer function as well as the number of the poles and zeros. Compared to the general Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL), this method reduces the amount of manual calculation considerably. Also, the circuit parameters forming poles and zeros can be obtained based on its converted SFG. In addition, it is helpful to further understand the formation of poles and zeros. The nested-miller frequency compensation (NMC), a three-stage operational amplifier, as an example, is presented to illustrate the specific application of this method.


Keywords: Mason’s Rule, Signal-Flow Graphs (SFG), Loop Search, Poles and Zeros


REFERENCES


  1. [1] Eschauzier, R. G. H., Kerklaan, L. P. T. and Huijsing, J. H., “A 100-MHz 100-dB Operational Amplifier with Multipath Nested Miller Compensation Structure,” IEEE Journal of Solid-State Circuits, Vol. 27, pp. 17091717 (1992). doi: 10.1109/4.173096
  2. [2] Leung, K. N. and Mok, P. K. T., “Nested Miller Compensation in Low-Power CMOS Design,” IEEE Transactions on Circuits and Systems II, Vol. 48, pp. 388 394 (2001). doi: 10.1109/82.933799
  3. [3] Huijsing, J. H. and Linebarger, D., “Low-Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges,” IEEE Journal of Solid-State Circuits, Vol. 20, pp. 11441150 (1985). doi: 10.1109/JSSC.1985. 1052452
  4. [4] You, F., Embabi, S. H. K. and Sanchez-Sinencio, E., “Multistage Amplifier Topologies with Nested Gm-C Compensation,” IEEE Journal of Solid-State Circuits, Vol. 32, pp. 20002011 (1997). doi: 10.1109/4.643658
  5. [5] Mason, S. J., “Feedback Theory - Some Properties of Signal Flow Graphs,” Proceeding of the IRE, Vol. 41, pp. 11441156 (1953). doi: 10.1109/JRPROC.1953. 274449
  6. [6] Mason, S. J., “Feedback Theory - Further Properties of Signal Flow Graphs,” Proceeding of the IRE, Vol. 44, pp. 920926 (1956). doi: 10.1109/JRPROC.1956. 275147
  7. [7] Ki, W. H., “Signal Flow Graph Analysis of Feedback Amplifiers,” IEEE Transactions on Circuits and Systems I, Vol. 47, pp. 926933 (2000). doi: 10.1109/81. 852948
  8. [8] Veerachary, M., “Modeling of Power Electronic Systems Using Signal Flow Graphs,” Proc. Int. Conf. IECON, pp. 53075312 (2006). doi: 10.1109/IECON. 2006.347660
  9. [9] Loera-Palomo, R., Morales-Saldana, J. A. and LeyvaRamos, J., “Signal Flow Graphs for Modelling of Switching Converters with Reduced Redundant Power Processing,” IET Power Electron, Vol. 5, pp. 1008 1016 (2012). doi: 10.1049/iet-pel.2012.0038
  10. [10] Chan, P. K. and Chen, Y. C., “Gain-Enhanced Feedforward Path Compensation Technique for Pole-Zero Cancellation at Heavy Capacitive Loads,” IEEE Transactions on Circuits and Systems II, Vol. 50, pp. 933 941 (2003). doi: 10.1109/TCSII.2003.820258