Test Slice Difference Technique for Low-Transition Test Data Compression

Jiann-Chyi  Rau; Po-Han  Wu; Wei-Lin Li

doi:10.6180/jase.2012.15.2.09

Test Slice Difference Technique for Low-Transition Test Data Compression

Jiann-Chyi Rau This email address is being protected from spambots. You need JavaScript enabled to view it.¹, Po-Han Wu¹ and Wei-Lin Li¹

¹Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C

Received: March 11, 2011
Accepted: November 22, 2011
Publication Date: June 1, 2012

Download Citation: ||https://doi.org/10.6180/jase.2012.15.2.09

ABSTRACT

This paper presents a low power strategy for test data compression and a new decompression scheme for test vectors. In our method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. Further, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one extra scan cell. In experimental results, the scheme that we presented achieve high compression ratio. The power consumption is also better compared with other well-known compression techniques.

Keywords: Test Data Compression, Low Power Testing, VLSI, Design for Testability (DFT)

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