An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

Jiann-Chyi  Rau; Chung-Lin  Wu; Po-Han Wu

doi:10.6180/jase.2011.14.1.06

An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

Jiann-Chyi Rau This email address is being protected from spambots. You need JavaScript enabled to view it.¹, Chung-Lin Wu¹ and Po-Han Wu¹

¹Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C.

Received: May 21, 2009
Accepted: November 23, 2009
Publication Date: March 1, 2011

Download Citation: ||https://doi.org/10.6180/jase.2011.14.1.06

ABSTRACT

Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS’89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.

Keywords: Clock Gating, Scan Test, Low Power Scan Test, Full-Scan Testing, Design for Testability, Yield Loss

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