Journal of Applied Science and Engineering

Published by Tamkang University Press


Impact Factor



Jiann-Chyi Rau This email address is being protected from spambots. You need JavaScript enabled to view it.1, Chung-Lin Wu1 and Po-Han Wu1

1Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C.


Received: May 21, 2009
Accepted: November 23, 2009
Publication Date: March 1, 2011

Download Citation: ||  


Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS’89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.

Keywords: Clock Gating, Scan Test, Low Power Scan Test, Full-Scan Testing, Design for Testability, Yield Loss


  1. [1] Girad, P., “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, Vol. 19, pp.8292 (2002).
  2. [2] Gerstendorfer, S. and Wunderlich, H. J., “Minimized Power Consumption for Scan-Based BIST,” Proc. IEEE Int’l Test Conf. (ITC), pp. 7784 (1999).
  3. [3] Zorian, Z., “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. IEEE VLSI Test Symp. (VTS), pp. 49 (1993).
  4. [4] Wang, S. and Gupta, S. K., “DS-LFSR: A New BIST TPG for Low Heat Dissipation,” Proc. IEEE Int’l Test Conf. (ITC), pp. 848857 (1997).
  5. [5] Rosinger, P., Al-Hashimi, B. M., and Nicolici, N., “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” IEEE Trans. Computer-Aided Design, Vol. 23, pp. 11421153 (2004).
  6. [6] Wang, S. and Gupta, S. K., “ATPG for Heat Dissipation Minimization for Scan Testing,” Proc. ACM/IEEE Design Auto. Conf. (DAC), pp. 614619 (1997).
  7. [7] Sankaralingam, R. and Touba, N. A., “Controlling Peak Power during Scan Testing,” Proc. IEEE VLSI Test Symp. (VTS), pp. 153159 (2002).
  8. [8] Badereddine, N., Girard, P., Pravossoudovitch, S., Landrault, C., Virazel, A., Wunderlich, H.-J., “Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics,” Proc. Design & Test of Integrated Systems in Nanoscale Technology. (DTIS), pp. 359364 (2006).
  9. [9] Girard, P., Landrault, C., Pravossoudovitch, S. and Severac, D., “Reducing Power Consumption during Test Application by Test Vector Ordering,” Proc. Int’l Circuits and Systems Symp. (ISCAS), Vol. 2, pp. 296 299 (1998).
  10. [10] Tseng, W.-D., “Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test,” IEE Proceedings on Computers and Digital Techniques, Vol. 152, pp. 609617 (2005).
  11. [11] Jung, J. M. and Chong, J. W., “Efficient Test Data Compression and Low Power Scan Testing in SoCs,” Electronics and Telecommunications Research Institute, Vol. 25, pp. 321327 (2003).
  12. [12] Saxena, J., Butler, K. M. and Whetsel, L., “An Analysis of Power Reduction Techniques in Scan Testing,” Proc. IEEE Int’l Test Conf. (ITC), pp. 670677 (2001).
  13. [13] Bonhomme, Y., Girard, P., Guiller, L., Landrault, C. and Pravossoudovitch, S., “A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores,” Proc. IEEE Asian Test Symp. (ATS), pp. 253 258 (2001).
  14. [14] Kim, H. S., Kim, C. G. and Kang, S., “ANew Scan Partition Scheme for Low-Power Embedded Systems,” Electronics and Telecommunications Research Institute, Vol. 30, pp. 412420 (2008).
  15. [15] Huang, T.-C. and Lee, K.-J., “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique,” IEEE Trans. Computer-Aided Design, Vol. 20, pp. 911917 (2001).
  16. [16] Alpaslan, E., Huang, Y., Lin, X., Cheng, W.-T. and Dworak, J., “Reducing Scan Shift Power at RTL,” Proc. IEEE VLSI Test Symp. (VTS), pp. 139146 (2008).
  17. [17] Lee, K. J., Huang, T. C. and Chen, J. J., “Peak-Power Reduction for Multiple-Scan Circuits during Test Application,” Proc. IEEE Asian Test Symp. (ATS), pp. 453458 (2000).
  18. [18] Nicolici, N. and Wen, X., “Embedded Tutorial on Low Power Test,” Proc. European Test Symp. (ETS), pp. 202207 (2007).
  19. [19] Wen, X., Kajihara, S., Miyase, K., Suzuki, T., Saluja, K., Wang, L.-T., Abdel-Hafez, K. and Kinoshita, K., “A New ATPG Method for Efficient Capture Power Reduction during Scan Testing,” Proc. IEEE VLSI Test Symp. (VTS), pp. 5863 (2006).
  20. [20] Wen, X., Yamashita, Y., Kajihara, S., Wang, L.-T., Saluja, K. and Kinoshita, K., “On Low-Capture-Power Test Generation for Scan Testing,” Proc. IEEE VLSI Test Symp. (VTS), pp. 265270 (2005).
  21. [21] Sankaralingam, R., Pouya, B. and Touba, N. A., “Reducing Power Dssipation during Test Using Scan Chain Disable,” Proc. IEEE VLSI Test Symp. (VTS), pp. 319 324 (2001).
  22. [22] Miyase, K. and Kajihara, S., “XID: Don’t Care Identification of Test Patterns for Combinational Circuit,” IEEE Trans. Computer-Aided Design, Vol. 23, pp. 321326 (2004).
  23. [23] Lee, H. K. and Ha, D. S., “Atalanta: an Efficient ATPG for Combinational Circuits,” Technical Report, 93-12, Dep’t of Electrical Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia (1993).