Journal of Applied Science and Engineering

Published by Tamkang University Press

1.30

Impact Factor

1.60

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Fun Ye This email address is being protected from spambots. You need JavaScript enabled to view it.1, Chih-Hao Kuei1 and Jen-Shiun Chiang1

1Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C.


 

Received: October 11, 2006
Accepted: October 22, 2007
Publication Date: June 1, 2008

Download Citation: ||https://doi.org/10.6180/jase.2008.11.2.10  


ABSTRACT


In recent years, computer applications have increased in the computational complexity. The speed requirement forces designers of general-purpose microprocessors to pay particular attention to implement the floating point unit (FPU). A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and radix-8 MROR (maximally redundant optimally recoded) signed digit number system. In NST division, the dividend and divisor must be prescaled. For the divider implementation, a signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A radix-8 MROR divider by TSMC 0.25 μm technology is thus designed and simulated. The simulation results show that the performance, hardware cost, and power consumption of the proposed divider is competitive to the conventional SRT divider.


Keywords: New Svoboda-Tung Division, Floating-Point Division, Prescaling, Radix-8, Signed Digit Number System


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