High-Speed Transition Detecting Circuits for On-Chip Interconnections

Hong-Yi Huang; Shih-Lun Chen

doi:10.6180/jase.2006.9.1.04

High-Speed Transition Detecting Circuits for On-Chip Interconnections

Hong-Yi Huang¹ and Shih-Lun Chen This email address is being protected from spambots. You need JavaScript enabled to view it.²

¹VLSI/CAD Laboratory, Department of Electronic Engineering, Fu-Jen Catholic University, Taiwan 242, R.O.C.
²Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan 300, R.O.C.

Received: March 29, 2005
Accepted: May 24, 2005
Publication Date: March 1, 2006

Download Citation: ||https://doi.org/10.6180/jase.2006.9.1.04

ABSTRACT

A transient sensitive trigger (TST) was used to reduce the RC delay time of the long interconnection in deep sub-micron (DSM) processes. The conventional TST circuit exhibits a voltage drop in threshold voltage during transitions, extending the delay time. This paper proposes new circuits called transition detecting circuits (TDCs) to overcome the drawbacks of the conventional TST. The proposed circuits yield 4574% shorter delay time than the conventional TST simulation using a 0.25 m CMOS process. The experiment results also show that the proposed TDCs are faster than the conventional TST. The proposed circuits can be applied to receiving long interconnect signals in high-speed VLSI design.

Keywords: High-Speed, Interconnections, Receivers, Deep Sub-Micron, Transition Detection

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