Application of Novel Digital Techniques for the Design of High Sensitivity Limiting Amplifier

Yang-Han Lee; Kuo-Ting Lin

doi:10.6180/jase.1999.2.4.07

Application of Novel Digital Techniques for the Design of High Sensitivity Limiting Amplifier

Electrical Engineering

Yang-Han Lee¹ and Kuo-Ting Lin¹

¹Department of Electrical Engineering Tamkang University Tamsui, Taipei Hsien, Taiwan, R. O. C.

Received: April 12, 1999
Accepted: May 31, 1999
Publication Date: December 1, 1999

Download Citation: ||https://doi.org/10.6180/jase.1999.2.4.07

ABSTRACT

In this letter we utilize the novel digital techniques (TW, DRMC, DS) to improve the sensitivity of the limiting amplifier. The Time Window (TW) technique can ignore the positive & negative trigger noises within the window close time. The Delay Racing Memory Counter (DRMC) technique can eliminate the positive trigger noises within the window open time. The Delay Sum (DS) technique can solve the negative trigger noise around the signal transition from low to high. The experimental results are also presented.

Keywords: Limiting Amplifier, Digital Techniques

REFERENCES

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[2]Yoon, T. and Jalali, B., “622Mbits/s CMOS Limiting Amplifier with 40dB Dynamic Range,” Electron. Lett., 32, pp.1920-1922 (1996).