Yung-Yuan Chen This email address is being protected from spambots. You need JavaScript enabled to view it.1 and Gene Eu Jan2
1Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan 300, R.O.C. 2Graduate Institute of Electrical Engineering, National Taipei University, Taipei, Taiwan, R.O.C.
Received: September 14, 2007 Accepted: July 15, 2009 Publication Date: June 1, 2010
This paper presents a comprehensive fault-tolerant verification platform which can be used to characterize the impact of fault attribute on error coverage. The core of the verification platform is the scenario-based fault injection tool that can inject the transient and permanent faults into VHDL models of digital systems at chip, RTL and gate levels during the design phase. Weibull fault distribution is employed to decide the time instant of fault injection. A new feature of our tool is to offer users the statistical analysis of the injected faults. The statistical data for each injection campaign exhibit the degree of fault severity, which represents a fault scenario (or called fault environment). By varying the fault attributes, such as the fault duration or fault-occurring rate, we can produce a variety of fault scenarios for the fault simulations. Such simulations can reveal the error coverage of the fault-robust systems under various fault environments. Two case studies with experiments of fault injection were conducted to show how the fault attribute affects the error coverage.
[1]Clark and D. Pradhan, “Fault Injection: A Method for Validating Computer-System Dependability,” IEEE Computer, 28(6), pp. 47-56, June 1995.
[2]C. Hsueh, T. K. Tsai and R. K. Iyer, “Fault Injection Techniques and Tools,” IEEE Computer, 30(4), pp. 75-82, April 1997.
[3]Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by A. Benso and P. Prinetto, Kluwer Academic Publishers, 2003.
[4]P. Acle, M. S. Reorda and M. Violante, “Early, Accurate Dependability Analysis of CAN-Based Networked Systems,” IEEE Design & Test of Computers, pp. 38-45, Jan.-Feb. 2006.
[5]A. Kanawati, N. A. Kanawati and J. A. Abraham, “FERRARI: A Flexible Software-Based Fault and Error Injection System,” IEEE Trans. on Computers, 44(2), pp. 248-260, Feb. 1995.
[6]Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, “Fault Injection into VHDL Models: The MEFISTO Tool,” FTCS-24, pp. 66-75, 1994.
[7]Folkesson, S. Svensson, and J. Karlsson, “A Comparison of Simulation-Based and Scan Chain implemented fault injection,”FTCS-28, pp. 284-293, 1998.
[8]Gil, R. Martínez, J. V. Busquets, J. C. Baraza, P. J. Gil, “Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System,” EDCC-3, pp. 191-208, 1999.
[9]K. Tsai, M. C. Hsueh, H. Zhao, Z. Kalbarczyk and R. K. Iyer, “Stress-Based and Path-Based Fault Injection,”IEEE Trans. On Computers, 48(11), pp. 1183-1201, Nov. 1999.
[10]R. Zarandi, S. G. Miremadi and A. Ejlali, “Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models,” 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 485-492, 2003.
[11]P. Siewiorek, R. S. Swarz, Reliable computer systems: design and evaluation (Burlington, MA: Digital Press, 1992).
[12]L. Hennessy, D. A. Patterson, Computer architecture: a quantitative approach (San Mateo, CA: Morgan Kaufmann, 1996).
[13]W. Johnson, Design and analysis of fault tolerant digital systems (Reading, MA: Addison-Wesley, 1989).
[14]A. Noufal, M. Nicolaidis, “A CAD Framework for Generating Self-Checking Multipliers Based on Residue Codes Design,” Automation and Test in Europe Conference and Exhibition, pp. 122-129, 1999.
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