Shuang-Yuan Chen This email address is being protected from spambots. You need JavaScript enabled to view it.1, Hung-Wen Chen1, Chia-Hao Tu1, Shao-Min Ho1, Lie-Chia Shie1 and Heng-Sheng Haung1

1Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, Taiwan 106, R.O.C.


Received: December 18, 2006
Accepted: June 8, 2007
Publication Date: March 1, 2008

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The capacity of flash memory increases rapidly due to the surging requirement of consumer electronics. This inevitably implies that the test time of these memories is becoming longer. As the test time is directly proportional to the test cost, test time reduction (TTR) has been becoming an important issue. In this paper, tuning the test voltages and frequencies of test program for TTR is presented for the first time. Each of programming, erasing and reading operations was evaluated for two types of NOR and one type of NAND flash memories. Based on the experimental results, the programming operation is the most time consuming among the three operations and can be effectively reduced by enhancing the test voltage and/or frequency. The reasons of the effectiveness are also provided. In the last, the optimal combinations of the supply voltages and test frequencies are proposed for each of the NOR and NAND-type memories.

Keywords: Test Time Reduction, TTR, Flash Memory, Memory Testing


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