Fun Ye1, Jen-Shiun Chiang This email address is being protected from spambots. You need JavaScript enabled to view it.1, Chun-Wen Chen1 and Yu-Chen Sung1
1Department of Electrical Engineering Tamkang University Tamsui, Taiwan 251, R.O.C.
Received: March 22, 2004 Accepted: May 21, 2004 Publication Date: September 1, 2004
This work presents a dynamic gate bias circuit for bias control to maximize power added efficiency based on the class-A two-stage power amplifier. The proposed circuits are composed of two NMOS transistors, a capacitor for coupling RF input signal, and four resistors for bias. The circuit is implemented by means of the bias control at the two-stage power amplifier to improve the overall power added efficiency and delivers 22dBm output power at 2.4 GHz. The circuit can improve power efficiency and linearity for small RF signals. The simulation indicates that the efficiency is improved more than 100%, and at 0 dBm the input signal has 515dB of IMD3 improvement compared with that without dynamic bias circuit. The output power of 22dBm at the output stage can be applied to the transceivers of IEEE 802.11b and Bluetooth applications [8].
Keywords: CMOS, Dynamic Bias Circuits, Linearity, Power Added Efficiency, Power Amplifier, RF.
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