Electrical Engineering

Hsin-Liang Chen1, Chi-Hsiung Wang2, and Jen-Shiun Chiang This email address is being protected from spambots. You need JavaScript enabled to view it.2

1Department of Electrical Engineering, Chinese Culture University; 55, Hwa-Kang Road, Yang-Ming-Shan, Taipei, Taiwan
2Department of Electrical Engineering, Tamkang University; No.151, Yingzhuan Rd. Tamsui, New Taipei City, Taiwan 25137 

 

Received: December 10, 2019
Accepted: May 29, 2020
Publication Date: December 1, 2020

 Copyright The Author(s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.


Download Citation: ||https://doi.org/10.6180/jase.202012_23(4).0008  

ABSTRACT

In this paper, a power minimizing strategy from a system- and circuit-perspective is developed for low-power reconfigurable multi-mode sigma-delta modulators. An experimental low-power modulator is designed for multi-mode systems with second- and fourth-order cascaded architectures. Several criteria are obtained to investigate the stability of the cascaded sigma-delta architecture. The proposed modulator can adapt to different system specifications with switchable stages and double-sampled techniques for better power efficiency. A test modulator chip is demonstrated with 0.13 μm CMOS technology. With the proposed strategy, the simulation results indicate that the designed fourth-order cascaded modulator will dissipate powers of 4.2, 11.3, and 20.2 mW and obtain a figure-of-merit (FoM) of 169, 149, and 157 at a supply voltage of 1.2 V for bandwidths 100kHz, 2 MHz, and 20 MHz, respectively.


Keywords: Cascaded; Reconfigurable; Sigma delta modulator; Multi-mode


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