Hsin-Liang Chen This email address is being protected from spambots. You need JavaScript enabled to view it.1, Chih-Hao Chen1, Wei-Bin Yang1 and Jen-Shiun Chiang1

1Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C.


 

Received: November 7, 2008
Accepted: February 11, 2009
Publication Date: December 1, 2009

Download Citation: ||https://doi.org/10.6180/jase.2009.12.4.09  


ABSTRACT


In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dBΩ and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplifier employs interleaving active feedback to achieve a differential voltage gain of 44.5 dB and a bandwidth of 10.3 GHz while consuming 226 mW. Both circuits are realized in 0.18-μm CMOS technology with a 1.8-V supply.


Keywords: Transimpedance Amplifier, Limiting Amplifier, Inducorless, Optical Communication


REFERENCES


  1. [1] Razavi, B., Design of Integrated Circuits for Optical Communications, McGraw Hill (2003).
  2. [2] Galal, S. and Razavi, B., “40-Gb/s Amplifier and ESD Protection Circuit in 0.18-m CMOS Technology,” IEEE J. Solid-State Circuits, Vol. 39, pp. 23892396 (2004).
  3. [3] Park, S. M. and Yoo, H. J., “1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications,” IEEE J. Solid-State Circuits, Vol. 39, pp. 112121 (2004).
  4. [4] Chan, C. T. and Chen, O. T. C., “Inductor-Less 10Gb/s CMOS Transimpedance Amplifier Using Source-Follower Regulated Cascode and Double Three-Order Active Feedback,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May, pp. 54875490 (2006).
  5. [5] Huang, H. Y., Chien, J. C. and Lu, L. H., “A 10-Gb/s Inductorless CMOS Limiting Amplifier with ThirdOrder Interleaving Active Feedback,” IEEE J. SolidState Circuits, Vol. 42, pp. 11111120 (2007).
  6. [6] Galal, S. and Razavi, B., “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-m CMOS Technology,” IEEE J. Solid-State Circuits, Vol. 38, pp. 21382146 (2003).
  7. [7] Chan, C. T. and Chen, O. T. C., “A 10Gb/s Optical Reciever Using Modified Regulated Cascade Scheme,” in Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), Vol. 1, pp.171174 (2005).
  8. [8] Wu, C. H., Lee, C. H., Chen, W. S. and Liu, S. I., “CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique,” IEEE J. Solid-State Circuits, Vol. 40, pp. 548552 (2005).
  9. [9] Chen, W. Z., Cheng, Y. L. and Lin, D. S., “A 1.8-V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-End,” IEEE J. Solid-State Circuits, Vol. 40, pp. 13881396 (2005).
  10. [10] Kim, H. H., Chandrasekhar, S., Burrus, Jr., C. A. and Bauman, J., “A Si BiCMOS Transimpedance Amplifier for 10-Gb/s SONET Receiver,” IEEE J. SolidState Circuits, Vol. 36, pp. 769776 (2001).
  11. [11] Kim, H. and Bauman, J., “A 12 GHz 30 dB Modular BiCMOS Limiting Amplifier for 10 Gb SONET Receiver,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb., pp. 160161 (2000).