In this paper we present an architecture for digital HDTV video decoding based on dual decoding data paths controlled in a block layer synchronization manner and an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, this scheme eliminates many problems, such as the memory access contention problem and the enormous extra local memory required. Our simulation shows that with an 81 MHz clock, our architecture uses fewer than the 332-cycle upper bound for MPEG-2 MP@HL real-time decoding for each macroblock.
Keywords: HDTY, Video compression, MPEG-2, DCT
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